Table Of Contents
Media Gateway Clocking
Clocking Basics
Clock Configuration
Displaying Clock Configuration
Clocking Guidelines
Qualifying a Clock Source
Switching to an Alternative Clock Source
Media Gateway Clocking
Clocking Basics
Network clocking is a means by which a clock signal is generated or derived and distributed through a node for the purpose of insuring synchronized network operation. Clocking and its configuration is at the gateway (or node) level. As such the clocking functions in an MGX 8850 media gateway reside in the PXM 45 card.
The MGX 8850 supports the following types of internal and external clock sources.
•
A BITS (Building Internal Timing Source) clock. This type is an external clock source connected to one of two RJ-48 type female connectors on the PXM-UI-S3 back card (see Figure A-1).
•A SETS (Synchronous Equipment Timing Source) clock. This type is an external clock source connected to one of two RJ-48 type female connectors on the PXM-UI-S3 back card (see Figure A-1).
•An external clock source derived from a service module line (for example, a VXSM line).
•An internal clock source consisting of a Stratum 3 clock circuit in the internal clock oscillator on the PXM back card - PXM-UI-S3.This clock source is distributed to all cards in the gateway.
If possible, the recommended clock source for a VXSM based MGX 8850 media gateway is BITS.
Note The two RJ-48 connectors for clock input are indicated as "4" in Figure A-1. One is labeled EXT CLK 1 and the other as EXT CLK 2. Each connector has an associated LED which is lit green when the clock source is active. If the LED is not lit, the clock source is either inactive or not in use.
From the above list of possible clock source types, the gateway can accept two clock sources. One source is designated as primary and is mandatory, the second source is designated a secondary and is optional. If a primary source fails, the secondary takes over.
If neither a primary or secondary source is specified, the default primary source becomes the Stratum 3 internal clock source (Free-running). Likewise, if no secondary is specified, the default secondary becomes the Stratum 3 internal clock source.
Figure A-1 PXM 45 UI S3 Back Card Connectors
Clock Configuration
Use the following steps to configure clocking on an MGX 8850 media gateway.
Step 1 Telnet onto the gateway. Check that you are logged in to the active PXM 45 card.
Step 2 Use the cnfclksrc command to configure the primary clock source.
The syntax of this command is:
cnfclksrc <priority> <portid>[ -bits { e1|t1 } ][ -revertive { enable|disable } ]
where:
priority This is either primary or secondary (default=primary)
portid The specification of the port ID depends upon the selected clock source.
If he BITS clock source is selected portid is specified as:
[shelf.]slot.port
shelf —always 1 and is optional.
slot—the logical slot number 7 for a BITS circuit on the PXM UI S3 (regardless of where the active PXM resides).
port—a logical number that indicates the upper or lower external clock connector on
the UI S3 back card. The logical port number for the upper connector is 35. The lower connector is 36.
If a VXSM is selected as the source, portid is specified as:
[shelf.]slot:subslot.port:subport
shelf—Always 1 and optional
slot—Slot number of the service module
subslot—Identifies the upper or lower bay of the back card, either a 1 for the upper bay or 2 for the lower bay (default is 1)
port—Line number on the service module back card plus 10. The specified line must already be active (see upln).
subport—Logical port number, plus 10. This value is the logical port (or ifNum) that you must assign using the addport command. Also, the logical port must be known to PNNI (see dsppnports).
Note When you specify a clock source on a VXSM card, the value 10 must be added to both the line and logical port numbers. For example, a primary clock source on a VXSM in slot 3, upper shelf, line 1, logical port 1 is specified as:
cnfclksrc primary 3:1.11:11
bits—This keyword parameter is required if slot number 7 and port number of 35 or 36 are specified in portid (indicating BITS as the clock source) Type the string -bits, followed by a space, then either e1 or t1.
revertive—An option that applies to only the BITS clock. Type the string -revertive, followed by the complete word enable or disable. The default is disable.
Step 3 Use the cnfclksrc command to configure the secondary clock source.
Step 4 Use the cnfclkparms command to configure the signal type and cable type for BITS sources (if applicable). The configuration applies to both (upper and lower) lines.
The syntax of this command is:
cnfclkparms <signal type> <cable type>
where:
signal type - [1-2]; 1 - data; 2 - syn (this parameter is not supported in this release)
cable type - [1-2]; 1 - twisted; 2 - coaxial
Note E1 lines can be either twisted pair or coaxial cable. T1 lines must always be specified as twisted pair.
Below is an example of a sequence of clock configuration commands.
8850japan.7.PXM.a > cnfclksrc primary 7.35 -bits t1 -revertive enable
8850japan.7.PXM.a > cnfclksrc secondary 7.36 -bits t1 -revertive enable
8850japan.7.PXM.a > cnfclkparms 1 1
Displaying Clock Configuration
On the PXM card, use the dspclksrcs command to display the clocking configuration.
8850japan.7.PXM.a > dspclksrcs
Primary clock type: bits t1
Primary clock source: 7.35
Primary clock status: bad
Primary clock reason: no clock
Secondary clock type: bits t1
Secondary clock source: 7.36
Secondary clock status: bad
Secondary clock reason: no clock
source switchover mode: revertive
On the VXSM card, use the dspln command to display clocking on a VXSM line. The values are loopclock (when clock is derived from a VXSM line) or local (when derived from BITS).
M8850_NY.3.VXSM.a > dspln 1.4
======================================================
======================================================
Interface Name : sonet.3.1.4
Operational Status : down
Time Elapsed(seconds) : 0
Loopback Config : lineLocal
Transmit Clock Source : localTiming
Frame Scramble : disabled
Section Transmit Trace : 000000000000000000000000000000000000000a
Section Expect Trace : 000000000000000000000000000000000000000a
Section Trace Failure : false
Section Received Trace : 000000000000000000000000000000000000000a
archer.5.VXSM.a > dspln 1.1
======================================================
======================================================
Interface Name : ds1.5.1.1
Time Elapsed(seconds) : 256
Loopback Config : dsx1NoLoop
Transmit Clock Source : localTiming
Trunk Condition Enable : false
Loopback Code Detection: false
Clocking Guidelines
•The network should have the least possible number of independent clock sources. The best arrangement is to have one network clock source that is distributed to all nodes in the network.
•There can only be one clock source per VXSM card.
•Different VXSM cards, in the same chassis or different chassis, that are part of the same network should get their clocks from sources traceable to the same reference source.
•Do not use separate clock sources unless you can confirm that they will remain closely phase locked. This prevents large changes in clock phase when a clock interface switchover occurs. It is best to take two separate feeds from the same clock source or same clock distribution system.
•Preferred clock sources for a VXSM equipped media gateway are:
–An external clock from the same source that the switch is connected to (BITS)
–An external clock from the switch (dedicated source or T1/E1 line)
•Prevent reflections that can produce noise. These are usually caused by:
–Unterminated connections
–Cables with long legs on the Y connections
Note MGX systems are designed to work with Y cables. The backup UI interface is always unterminated until it becomes the primary. This mode of operation insures that only one of the legs of a Y cable is terminated preventing both terminations from being on at the same time. If both terminations are on at the same time, the termination resistance (impedance) becomes half its expected value.
–Too many connectors in the line path
•Use good quality wiring techniques for clock source cables. Use shielded UTP if possible, UTP at a minimum, for balanced (100 or 120 ohm) cables. Make sure you have good grounds on the unbalanced coax clock cables. Keep clock cables as short as possible.
•Clocking problems typically cause Packet Errors, HEC (Header Error Check) errors, PLCP (Physical Layer Convergence Protocol) errors, or frame-sync errors. The error depends upon the type of trunk interface used.
•Clock slips on voice circuits can result in dropped calls, hissing, scratchiness, and echo problems.
Qualifying a Clock Source
When a primary clock source is configured it is qualified by sampling the clock for its frequency at 1 sample per second and analyzing 24 batches each consisting of 16 samples. For a clock to be qualified as a "narrow-band compliant" source, all 16 samples in a batch must have a frequency of within ±4.66 parts per million. after a clock source is qualified, it is deemed Lockable.
A primary Lockable clock source is monitored at one second intervals to ensure that it continues to be qualified. A clock source configured as secondary, is also qualified as Lockable but it is not monitored (unless it becomes the primary source).
A clock source is considered bad if there is a loss-of-activity/loss-of-signal or it becomes Unlockable. When the active clock source is detected to be bad, the active clock source is switched to an alternative good clock source.
Switching to an Alternative Clock Source
Table A-1 summarizes the choice of the alternative clock source:
Table A-1 Next Active Clock Source
Configuration
|
Current Active Clock Source
|
Next Active Clock Source
|
Only Primary
|
Primary
|
Holdover if enough samples available. Otherwise, Free-running (internal local oscillator).
|
Primary and Secondary
|
Primary
|
Secondary.
|
Secondary
|
Holdover if enough samples available. Otherwise, Free-running.
|
Holdover (stored samples)
|
Free-running.
|
Free-running
|
None.
|
The decisions to switch from a bad clock source to an alternative clock source depend on the current active clock source, the nature of failure and the configuration.
Basically there are three major situations.
•Only a primary clock source is configured.
•A primary and secondary clock source are configured with auto-revertive mode enabled.
•A primary and secondary clock source are configured with auto-revertive mode disabled.
Note Auto-revertive mode monitors the failed primary clock source and automatically reverts to that source if it recovers and becomes qualified. The auto-revertive mode is available only if the primary clock source is configured to be an external BITS clock source.
Table A-2 summarizes failure scenarios and recovery actions taken when only a primary clock source is configured:
Table A-2 Clock Failure and Recovery: Primary Source Only
Clock Source Failure
|
Actions
|
Primary is the Active clock source and is in LOA/LOS
|
Raise minor alarm to indicate that primary clock source is lost.
Switch to Holdover if enough samples available.
Switch to free-running if enough samples are not available.
Raise major alarm to indicate that the node's clock is in holdover or free-running mode.
Continue to monitor primary.
Once it is out of LOA/LOS, switch to free-running, if it is in holdover mode. Then, re-qualify the primary and revert to the primary when becomes Lockable and clear the alarms.
|
Primary clock source is the Active clock source and it becomes Unlockable
|
Raise minor alarm to indicate that the primary clock is lost.
Switch to free-running.
Raise major alarm to indicate that the clock is in free-running mode.
Note: The primary clock source will be monitored. If it becomes lockable, the primary clock source will be the active clock source This behavior is possible in Release 4.0 and later.
|
Holdover mode time expires (beyond 24 hours)
|
Switch to free-running.
Continue to monitor the primary clock source. After it goes out of LOA/LOS, requalify the primary clock source and switch to the primary when it becomes Lockable and clear the alarms.
|
In Free-running mode, local oscillator fails.
|
TBD: Should raise a critical alarm.
Note: This may cause a traffic outage if this happens on the Active PXM. Manual PXM switchover is necessary to recover from the outage. If this happens on the Standby PXM, failure/manual switchover to the Standby PXM may cause an outage.
|
Table A-3 summarizes failure scenarios and recovery actions taken when both a primary clock sources are configured with Autorevertive enabled.
Table A-3 Clock Failure/Recovery: Primary and Secondary—Revertive Enabled
Clock Source Failure
|
Action
|
Primary clock source is the active clock source and it goes into LOA/LOS
|
Raise minor alarm to indicate the primary clock source is lost.
Switch to secondary clock source if it is not in LOA/LOS and is Lockable. The secondary clock source becomes the active clock source.
Switch to Holdover mode if secondary clock source is not available, and there are enough clock samples collected from the primary clock source.
Switch to Free-running mode and use the internal oscillator if neither the secondary clock source is available nor switching to Holdover mode is possible.
Raise major alarm if the clock is in holdover or free-running mode.
Once the primary goes out of LOA/LOS, switch to free-running, raise major alarm to indicate that the clock is in free-running mode and start re-qualifying the primary clock source. Switch to the primary once it becomes Lockable after the re-qualification procedure and clear the alarms.
|
Primary clock source is the active clock source and it enters out-of-lock state. That is, the frequency of the clock sample goes out of range of ±4.66 ppm.
|
Raise minor alarm to indicate that the primary clock is lost.
Continue monitor the primary clock source.
If 12 out of 16 samples have the frequency with in the range of ±4.66 ppm, declare it Lockable again and clear the alarm.
Otherwise, if more than 6 samples have the frequency with in the range of ±4.66 ppm, declare it Unlockable and start the re-qualification process. During this re-qualification, switch to the secondary or the free-running, if secondary is not available. Raise major alarm if it is in free-running mode. Once the re-qualification process is complete and the primary is Lockable, revert to the primary, else, declare the primary Unlockable.
Otherwise (if there only less than 6 samples having the frequency with in the ±4.66 ppm), declare the primary Unlockable.
|
Primary clock source is the active clock source and it becomes Unlockable after requalification in out-of-lock state failed.
Note: The primary clock source enters out-of-lock state before becoming Unlockable. If it became Unlockable after requalification, the active clock should have been already switched to the secondary or the free-running mode.
|
Note: The primary clock source is monitored/qualified, and switched over to the primary clock source if the clock source is good.
|
Primary clock source is the active clock source and it becomes Unlockable because the number of samples with frequency with in ±4.66 ppm out of the 16 collected samples is less than 6.
Note: In this case, the active clock source is still the primary and is in the out-of-lock state.
|
Switch to secondary clock source if it is not in LOA/LOS and is lockable. The secondary clock source becomes the active clock source.
Switch to Free-running mode and use the internal oscillator if the secondary clock source is not available.
Raise major alarm if the clock is in free-running mode.
|
Secondary clock source is the active clock source and it goes into LOA/LOS.
|
Raise minor alarm to indicate that secondary clock source is lost.
Switch to holdover mode if there are enough samples.
Switch to Free-running if there are not enough samples to switch to holdover mode.
Raise major alarm to indicate that the active clock is either holdover or free-running mode.
Switch back to the primary or the secondary once one of them becomes available.
|
Secondary clock source is the active clock source and it enters out-of-lock state. That is, the frequency of the clock sample goes out of ±4.66 ppm range.
|
Raise minor alarm to indicate that the secondary clock is lost.
Continue monitor the secondary clock source.
If 12 out of 16 samples have the frequency with in the range of ±4.66 ppm, declare it lockable again and clear the alarm.
Otherwise, if more than 6 samples have the frequency with in the range of ±4.66 ppm, declare it Unlockable and start the re-qualification process. During this requalification, switch to the free-running mode. Raise major alarm to indicate that it is in free-running mode. Once the requalification process is complete and the secondary is lockable, revert to the secondary, else, declare the secondary Unlockable.
Otherwise (if there only less than 6 samples having the frequency with in the ±4.66 ppm), declare the secondary Unlockable.
|
Secondary clock source is the active clock source and it becomes Unlockable after requalification in out-of-lock state failed.
Note: The secondary clock source enters out-of-lock states before becoming Unlockable. If it became Unlockable after requalification, the active clock should have been already switched to the free-running mode.
|
Note: The primary and the secondary clock sources are no longer monitored/qualified and no switchover to the secondary or the primary clock source occurs. The clock sources must be manually reconfigured to initiate the switchover to the primary or the secondary clock source.
|
Secondary clock source is the active clock source and it becomes Unlockable because the number of samples with frequency with in ±4.66 ppm out of the 16 collected samples is less than 6.
Note: In this case, the active clock source is still the secondary and is in the out-of-lock state.
|
Switch to Free-running mode and use the internal oscillator.
Raise major alarm to indicate that the clock is in free-running mode.
Note: The primary and secondary clock sources are no longer monitored/qualified and no switchover to the primary or the secondary clock source occurs. The clock sources needs to be manually reconfigured to initiate the switchover to the primary or the secondary clock source.
|
Holdover expires (more than 24 hours since clock source is switched to the holdover mode)
|
Raise major alarm.
Switch to free-running mode.
|
In Free-running mode, local oscillator fails.
|
TBD: Should it raise critical alarm?
Note: This may cause a traffic outage if this happens on the Active PXM. Switchover to Standby PXM should be initiated manually to recover from the outage. If this happens on the Standby PXM, failure/manual switchover to the Standby PXM may cause an outage.
|
Table A-4 summarizes failure scenarios and recovery actions taken when both a primary clock sources are configured with Auto-revertive disabled
Table A-4 Clock Failure/Recovery: Primary and Secondary—Revertive Disabled
Clock Source Failure
|
Action
|
Primary clock source is the active clock source and it enters LOA/LOS.
|
Raise minor alarm to indicate that primary clock source is lost.
Switch to secondary clock source if it is not in LOA/LOS and is lockable. The secondary clock source becomes the active clock source.
Switch to Holdover mode if secondary clock source is not available, and there were enough clock samples collected from the primary clock source.
Switch to Free-running mode and use the internal oscillator if neither the secondary clock source is available nor switching to Holdover mode is possible.
Raise major alarm if the active clock is in holdover or free-running mode.
After the primary comes out of LOA/LOS, initiate the requalification of the primary. If the active clock source is in holdover or free-running mode, then, switch to the primary after the requalification process is complete and is lockable.
|
Primary clock source is the active clock source and it enters out-of-lock states. That is, the frequency of the clock sample goes out of ±4.66 ppm range.
|
Raise minor alarm to indicate that the primary clock is lost.
Continue monitor the primary clock source.
If 12 out of 16 samples have the frequency with in the range of ±4.66 ppm, declare it lockable again and clear the alarm.
Otherwise, if more than 6 samples have the frequency with in the range of ±4.66 ppm, declare it Unlockable and start the re-qualification process. During this requalification, switch to the secondary or the free-running, if secondary is not available. Raise major alarm if it is in free-running mode. After the requalification process is complete and the primary is lockable, revert to the primary if the active clock source is in free-running mode. If the primary is not lockable, declare the primary Unlockable.
Otherwise (if there only less than 6 samples having the frequency with in the ±4.66 ppm), declare the primary Unlockable.
|
Primary clock source is the active clock source and it becomes Unlockable.
|
Raise the alarm.
Switch to secondary clock source if it is not in LOA/LOS and lockable. The secondary clock source becomes the active clock source.
Switch to Free-running mode and use the internal oscillator if the secondary clock source is not available.
|
Secondary clock source is the active clock source and it goes into LOA/LOS.
|
Raise the alarm.
Switch to Free-running.
Switch back to the primary or the secondary once one of them becomes available.
|
Secondary clock source is the active clock source and it becomes Unlockable.
|
Raise the alarm.
Switch to Free-running.
Switch back to the primary or the secondary once one of them becomes available.
|
In Free-running mode, local oscillator fails.
|
Raise the alarm.
Note: This may cause a traffic outage if this happens on the Active PXM and the PXM switchover is not initiated manually. If this happens on the Standby PXM, failure/manual switchover to the Standby PXM may cause an outage.
|
