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Overview
Hardware designs increasingly favor multiple cores per CPU die over increased speed, resulting in number fabrication constraints. This creates a new Moore's Law in which doubling core counts every 10 months.
Modern software designs use virtualization to maximize utilization and flexibility across specific hardware implementations with efficient isolation amongst processes. These two new technology trends can be combined to enable dense efficient processing of network applications. To leverage the combination of these architectural shifts it will be necessary to use appropriate forms of loose and tightly coupled parallel algorithms and implementations.
For instance, in a single stream of packets, multiple independent flows can be identified and processed in parallel. Also some network algorithms can be implemented on a tightly coupled complex of SMP configured processors to simultaneously update portions of a shared memory image. In addition, common networking operations on a given flow may be performed in a loosely coupled pipelined fashion (e.g., packet parsing, classification, processing, etc.) with each step dedicated to a given virtual machine. Dynamic allocation of hardware and software resources can enable independent applications to be simply and efficiently scheduled and run without mutual interference.
Optimization of such applications has traditionally been implemented either using special purpose hardware (e.g., ASICs) or general purpose CPUs. ASICs deliver high performance but sacrifice flexibility; general purpose CPUs allow for flexibility at the expense of performance. The recent emergence and popularity of multicore CPU substrates overlaid with a virtualization hypervisor and virtual machines provides opportunities for solutions that optimize networking applications with a better tradeoff between flexibility and performance.
Parallelism is generally more complex to program. The purpose of this research area is to investigate new programming paradigms that enable the exploitation of the parallelism offered by multi-core architectures.
Hardware Architecture
This subtopic aims at defining 'models' of multicore architectures for analysis and experimentation purposes. Ideally there should be at least three models defined:
- An abstract model, not targeted to any specific hardware or operating system;
- A server model, targeted to Linux on commodity server hardware;
- A Network Processor oriented model.
Those models would be useful, for example, to assess the performance of the memory/cache subsystem with various workloads.
If your research topic doesn't directly address any of the proposed RFPs please submit it as a generic proposal for this area.
If you have comments, questions or feedbacks related to this area please don't hesitate to contact us at research-multicore@cisco.com
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